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CMOS Analog Circuit Design Page 8.0-1 CHAPTER 8 - CMOS COMPARATORS Chapter Outline 8.1 Characterization of Comparators 8.2 Two-Stage, Open-Loop Comparators 8.3 Other Open-Loop Comparators 8.4 Improving the Performance of Open-Loop Comparators 8.5 Discrete-Time Comparators 8.6 High-Speed Comparators 8.7 Summary Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-1 SECTION 8.1 - CHARACTERIZATION OF COMPARATORS Circuit Symbol for a Comparator vP vN + - vO Fig. 8.1-1 Static Characteristics • Gain • Output high and low states • Input resolution • Offset • Noise Dynamic Characteristics • Propagation delay • Slew rate Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-2 Noninverting and Inverting Comparators The comparator output is binary with the two-level outputs defined as, VOH = the high output of the comparator VOL = the low level output of the comparator Voltage transfer function of an Noninverting and Inverting Comparator: vo vo VOH VOH vP-vN vP-vN VOL VOL Noninverting Comparator Inverting Comparator Fig. 8.1-2A Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-3 Static Characteristics - Zero-order Model for a Comparator Voltage transfer function curve: vo VOH vP-vN VOL Fig. 8.1-2 Model: vP + vP-vN vN f0(vP-vN) + vO - Comparator VOH for (vP-vN) > 0 f0(vP-vN) = VOL for (vP-vN) < 0 - Fig. 8.1-3 VOH-VOL where ∆V is the input voltage change ∆V ∆V→0 Gain = Av = lim Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-4 Static Characteristics - First-Order Model for a Comparator Voltage transfer curve: vo VOH VIL vP-vN VIH VOL Fig. 8.1-4 where VIH = smallest input voltage at which the output voltage is VOH (noninverting comparator) VIL = largest input voltage at which the output voltage is VOL (noninverting comparator) Model: vP + vP-vN f1(vP-vN) - - vN + vO Comparator VOH for (vP-vN) > 0 f1(vP-vN) = Av(vP-vN) for VIL< (vP-vN)<VIH VOL for (vP-vN) < 0 Fig. 8.1-5 VOH − VOL The voltage gain is Av = V − V IH IL Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-5 Static Characteristics - First-Order Model including Input Offset Voltage Voltage transfer curve: vo VOH VOS VIL vP-vN VIH VOL Fig. 8.1-6 VOS = the input voltage necessary to make the output equal VOH+VOL when vP = vN. 2 Model: vP +vP' ±VOSv '-v ' P N vN -v ' N f1(vP'-vN') Comparator + vO Fig. 8.1-7 Other aspects of the model: ICMR = input common mode voltage range (all transistors remain in saturation) Rin = input differential resistance Ricm = common mode input resistance Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-6 ;; Static Characteristics - Comparator Noise Noise of a comparator is modeled as if the comparator were biased in the transition region. vo VOH Rms Noise vP-vN VOL Transition Uncertainty Fig. 8.1-8 Noise leads to an uncertainty in the transition region which causes jitter or phase noise. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-7 Dynamic Characteristics - Propagation Time Delay Rising propagation delay time: vo VOH V +V vo = OH OL t 2 VOL vi = vP-vN VIH tp VIL V +V vi = IH IL 2 t Fig. 8.1-9 Rising propagation delay time + Falling propagation delay time Total propagation delay time = 2 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-8 Dynamic Characteristics - Single-Pole Response Model: Av(0) Av(0) = sτ +1 Av(s) = s c ωc + 1 where Av(0) = dc voltage gain of the comparator 1 ω c = τ = -3dB frequency of the comparator or the magnitude of the pole c Step Response: vo(t) = Av(0) [1 - e-t/τc]Vin where Vin = the magnitude of the step input. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-9 Dynamic Characteristics - Propagation Time Delay The rising propagation time delay for a single-pole comparator is: VOH-VOL = Av(0) [1 - e-tp/τc]Vin → tp = τc ln 2 1 1 - VOH˚-VOL 2Av(0)Vin Define the minimum input voltage to the comparator as, VOH -VOL Vin(min) = A (0) → tp = τc ln v 1 Vin(min) 1- 2Vin Define k as the ratio of the input step voltage, Vin, to the minimum input voltage, Vin(min), Vin 2k k = V (min) → tp = τc ln 2k-1 in Thus, if k = 1, tp = 0.693τc. Illustration: vout VOH vin + - Vin > Vin(min) vout VOH+VOL 2 Vin = Vin(min) VOL 0 t t (max) 0 p p t Fig. 8.1-10 Obviously, the more overdrive applied to the input, the smaller the propagation delay time. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.1-10 Dynamic Characteristics - Slew Rate of a Comparator If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by the slew rate. Slew rate comes from the relationship, dv i = C dt where i is the current through a capacitor and v is the voltage across it. If the current becomes limited, then the voltage rate becomes limited. Therefore for a comparator that is slew rate limited we have, ∆V VOH- VOL tp = ∆T = SR = 2·SR where SR = slew rate of the comparator. Chapter 8 - CMOS Comparators (5/1/01) CMOS Analog Circuit Design © P.E. Allen, 2001 Page 8.1-11 Example 8.1-1 - Propagation Delay Time of a Comparator Find the propagation delay time of an open loop comparator that has a dominant pole at 103 radians/sec, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltage swing of 1V. Assume the applied input voltage is 10mV. Solution The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV input is 100 times larger than vin(min) giving a k of 100. Therefore, we get 1 2·100 200 tp = 103 ln2·100-1 = 10-3 ln199 = 5.01µs For slew rate considerations, we get 1 tp = 2·1x106 = 0.5µs Therefore, the propagation delay time for this case is the larger or 5.01µs. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-1 SECTION 8.2 - TWO-STAGE, OPEN-LOOP COMPARATORS Two-Stage Comparator An important category of comparators are those which use a high-gain stage to drive their outputs between VOH and VOL for very small input voltage changes. The two-stage op amp without compensation is an excellent implementation of a high-gain, open-loop comparator. VDD M3 vin + M1 M4 M6 vout M2 CL + VBias - Chapter 8 - CMOS Comparators (5/1/01) CMOS Analog Circuit Design M7 M5 VSS Fig. 8.2-1 © P.E. Allen, 2001 Page 8.2-2 Performance of the Two-Stage, Open-Loop Comparator We know that the performance should be similar to the uncompensated two-stage op amp of Chapter 6. Emphasis on comparator performance: • Maximum output voltage 8I7 1 - β (V -V (min)-|V |)2 VOH = VDD - (VDD-VG6(min)-|VTP|)1 6 DD G6 TP • Minimum output voltage VOL = VSS • Small-signal voltage gain gm1 gm6 Av(0) = g +g g +g ds2 ds4 ds6 ds7 • Poles Input: -1 p1 = C (g +g ) I ds2 ds4 Output: -1 p2 = C (g +g ) II ds6 ds7 • Frequency response Av(0) Av(s) = s s p + 1 p + 1 1 2 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-3 Example 8.2-1 - Performance of a Two-Stage Comparator Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, for the two-stage comparator shown in Fig. 8.2-1. Assume that this comparator is the circuit of Ex. 6.3-1 with no compensation capacitor, Cc, and the minimum value of VG6 = 0V. Also, assume that CI = 0.2pF and CII = 5pF. Solution Using the above relations, we find that VOH = 2.5 - (2.5-0-0.7) 1 1- 8·234x10-6 = 2.2V -6 2 · 50x10 38(2.5-0-0.7) The value of VOL is -2.5V. The gain was evaluated in Ex. 6.3-1 as Av(0) = 7696. Therefore, the input resolution is VOH-VOL 4.7V Vin(min) = A (0) = 7696 = 0.611mV v Next, we find the poles of the comparator, p1 and p2. From Ex. 6.3-1 we find that p1 = gds2 + gds4 15x10-6(0.04+0.05) = = 6.75x106 (1.074MHz) CI 0.2x10-12 p2 = gds6 + gds7 95x10-6(0.04+0.05) = = 1.71x106 (0.272MHz) CII 5x10-12 and Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-4 Linear Step Response of the Two-Stage Comparator The step response of a circuit with two real poles (p1 ≠ p2) is, p2e-tp1 p1e-tp2 vout(t) = Av(0)Vin1 + p -p - p -p 1 2 1 2 Normalizing gives, vout(t) m 1 vout’(tn ) = A (0)V = 1 - m-1e-tn + m-1e-mtn v in where p2 m = p ≠ 1 and 1 t tn = tp1 = τ 1 If p1 = p2 (m =1), then tn vout’(tn) = 1 - p1e-tn - p e-tn = 1 - e-tn - tne-tn 1 where p1 = 1. 1 Normalized Output Voltage m=4 0.8 m=2 m = 1 m = 0.5 m = 0.25 0.6 0.4 p2 m= p 1 0.2 0 0 Chapter 8 - CMOS Comparators (5/1/01) 2 4 6 8 Normalized Time (tn = tp1 = t/τ1) 10 Fig. 8.2-2 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-5 Linear Step Response of the Two-Stage Comparator - Continued The above results are valid as long as the slope of the linear response does not exceed the slew rate. • Slope at t = 0 is zero • Maximum slope occurs at (m ≠1) ln(m) tn(max) = m-1 and is dvout’(tn(max)) m -ln(m) ln(m) = m-1exp m-1 - exp-m m-1 dtn • For the two-stage comparator using NMOS input transistors, the slew rate is I7 SR- = C II I6-I7 β6(VDD-VG6(min)-|VTP|)2 - I7 SR+ = C = CII II Chapter 8 - CMOS Comparators (5/1/01) CMOS Analog Circuit Design © P.E. Allen, 2001 Page 8.2-6 Example 8.2-2 - Step Response of Ex. 8.2-1 Find the maximum slope of Ex. 8.2-1 and the time at which it occurs if the magnitude of the input step is vin(min). If the dc bias current in M7 is 100µA, at what value of load capacitance, CL would the transient response become slew limited? If the magnitude of the input step is 100vin(min), what would be the new value of CL at which slewing would occur? Solution The poles of the comparator were given in Ex. 8.2-1 as p 1 = -6.75x106 rads/sec. and p 2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous expressions, the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p1| gives t(max) = 0.272µs. The slope of the transient response at this time is found as dvout’(tn(max)) = -0.338[exp(-1.84) - exp(-0.253·1.84)] = 0.159 V/sec dt n Multiplying the above by |p1| gives dvout’(t(max)) = 1.072V/µs dt Therefore, if the slew rate of the comparator is less than 1.072V/µs, the transient response will experience slewing. Also, if the load capacitance, CL, becomes larger than 100µA/1.072V/µs or 93.3pF, the comparator will experience slewing. If the comparator is overdriven by a factor of 100vin(min), then we must unnormalize the output slope as follows. vin dvout’(t( max)) dvout’(t( max)) = v (min) = 100·1.072V/µs = 107.2V/µs dt dt in Therefore, the comparator will now slew with a load capacitance of 0.933pF. For large overdrives, the comparator will generally experience slewing. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-7 Propagation Delay Time (Non-Slew) To find tp, we want to set 0.5(VOH-VOL) equal to vout(tn). However, vout(tn) is given as m 1 vout(tn) = Av(0)Vin 1 - m-1e-tn + m-1e-mtn which can’t be easily solved so approximating the step response as a power series gives tn2 m2tn2 mtn2Av(0)Vin m 1 vout(tn) ≈ Av(0)Vin1 - m-11-tn+ 2 + ··· + m-11-mtn+ 2 +··· ≈ 2 Therefore, set vout(tn) = 0.5(VOH-VOL) VOH+VOL mtpn2Av(0)Vin ≈ 2 2 or Vin(min) 1 mVin = mk This approximation is particularly good for large values of k. tpn ≈ VOH+VOL mAv(0)Vin = Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-8 Example 8.2-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew) Find the propagation time delay of the comparator of Ex. 8.2-1 if Vin = 10mV, 100mV and 1V. Solution From Ex. 8.2-1 we know that Vin(min) = 0.611mV and m = 0.253. For V in = 10mV, k = 16.366 which gives tpn ≈ 0.491. The propagation time delay is equal to 0.491/6.75x106 or 72.9nS. This corresponds well with Fig. 8.2-2 where the normalized propagation time delay is the time at which the amplitude is 1/2k or 0.031 which corresponds to tpn of approximately 0.5. Similarly, for V in = 100mV and 1V we get a propagation time delay of 23ns and 7.3ns, respectively. 1 Normalized Output Voltage m=4 0.8 m=2 m = 1 m = 0.5 m = 0.25 0.6 0.4 p2 m= p 1 0.2 1 = 0.031 0 2k 0 2 4 6 8 0.52 Normalized Time (tn = tp1 = t/τ1) tp = 0.52 = 77ns 6.75x106 Chapter 8 - CMOS Comparators (5/1/01) 10 Fig. 8.2-2A © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-9 Initial Operating States for the Two-Stage, Open-Loop Comparator What are the initial operating states for the following comparator? VDD M3 i4 M4 vo1 i1 i2 i3 vG1 M1 M6 CI vout vG2 M2 CII ISS + VBias - M7 M5 VSS Fig. 8.2-3 1.) Assume vG2 = VREF and vG1>VREF with i1 < ISS and i2>0. Initially, i4 > i2 and vo1 increases, M4 becomes active and i4 decreases until i3 = i4. vo1 is in the range of, vG1 > VREF, i1 < ISS and i2 > 0 VDD - VSD4(sat) < vo1 < VDD, and the value of vout is vout ≈ VSS vG1 > VREF, i1 < ISS and i2 > 0 2.) Assume vG2 = VREF and vG1 >>VREF, therefore i1 = ISS and i2 = 0 which gives and vout = VSS vo1 = VDD Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-10 Initial Operating States - Continued 3.) Assume vG2 = VREF and vG1 < VREF with i1>0 and i2<ISS. Initially, i4 < i2 and vo1 decreases. When vo1 ≤ VREF - VTN, M2 becomes active and i2 decreases. When i1 = i2 = ISS/2 the circuit stabilizes and vo1 is in the range of, VREF - VGS2 < vo1 < VREF - VGS2 + VDS2(sat) or VS2 < vo1 < VS2 + VDS2(sat), vG1 < VG2, i1 > 0 and i2 < ISS For the above conditions, vout = VDD - (VDD-vo1-|VTP|)1 1- β7ISS β5β6(VDD˚-vo1-|VTP|)2 4.) Assume vG2 = VREF and vG1 << VREF, therefore i2 = ISS and i1 = 0. Same as in 3.) but now as vo1 approaches vS2 with ISS/2 flowing, the value of vGS2 becomes larger and M5 becomes active and ISS decreases. In the limit, ISS → 0,vDS2 ≈ 0 and vDS5 ≈ 0 resulting in vo1 ≈ VSS and vout = VDD - (VDD-VSS-|VTP|)1 - Chapter 8 - CMOS Comparators (5/1/01) 1- β7ISS β5β6(VDD-VSS-|VTP|)2 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-11 Initial Operating States - Continued 5.) Assume vG1 = VREF and vG2>VREF with i2 < ISS and i1>0. Initially, i4 < i2 and vo1 falls, M2 becomes active and i2 decreases until i1 = i2 = ISS/2. Therefore, VREF - VGS2(ISS/2) < vo1 < VREF - VGS2(ISS/2) +VDS2(sat) or VS2(ISS/2) < vo1 < VS2(ISS/2) + VDS2(sat), vG2 > VREF, i1 > 0 and i2 < ISS and the value of vout is vout = VDD - (VDD-vo1-|VTP|)1 - 1- β7ISS 2 β5β6(VDD˚-vo1-|VTP|) 6.) Assume that vG1 = VREF and vG2 >> VREF. When the source voltage of M1 or M2 causes M5 to be active, then ISS decreases and vo1 ≈ VSS and vout = VDD - (VDD-VSS-|VTP|)1 1- β7ISS β5β6(VDD -VSS-|VTP|)2 7.) Assume vG1 = VREF and vG2 < VREF and i1 <ISS and i2 > 0. Consequently, i4>i2 which causes vo1 to increase. When M4 becomes active i4 decreases until i2 = i4 at which vo1 stabilizes at VDD - VSD4(sat) < vo1 < VDD, vG2 < VREF, i1 < ISS and i2 > 0 M6 will be off under these conditions and vout ≈ VSS. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-12 Initial Operating States - Continued 8.) Finally if vG2 <<VREF, then i1 = ISS and i2 =0 and vo1 ≈ VDD and vout ≈ VSS. Summary of the Initial Operating States of the Two-Stage, Open-Loop Comparator using a N-channel, Source-coupled Input Pair: Initial State of vo1 Initial State of vout vG1>VG2, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD V SS vG1>>VG2, i1=ISS and i2=0 VDD V SS Conditions vG1<VG2, i1>0 and i2<ISS vo1=VG2-VGS2,act(ISS/2), ≈VSS if M5 act. Eq. (19), Sec. 5.1 for PMOS vG1<<VG2, i1>0 and i2<ISS V SS Eq. (19), Sec. 5.1 for PMOS vG2>VG1, i1>0 and i2<ISS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) Eq. (19), Sec. 5.1 for PMOS vG2>>VG1, i1>0 and i2<ISS VG1-VGS1(ISS/2) , ≈VSS if M5 active Eq. (19), Sec. 5.1 for PMOS vG2<VG1, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD V SS VDD V SS vG2<<VG1, i1<<ISS and i2>0 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-13 Trip Point of an Inverter In order to determine the propagation delay time, it is necessary to know when the second stage of the two-stage comparator begins to “turn on”. Second stage: VDD M6 i6 + vin - vout i7 M7 VBias VSS Fig. 8.2-4 Trip point: Assume that M6 and M7 are saturated. (We know that the steepest slope occurs for this condition.) Equate i6 to i7 and solve for vin which becomes the trip point. ∴ vin = VTRP = VDD - |VTP| - KN(W7/L7) KP(W6/L6) (VBias- VSS -VTN) Example: If W7/L7 = W6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the circuit above is VTRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V Chapter 8 - CMOS Comparators (5/1/01) CMOS Analog Circuit Design © P.E. Allen, 2001 Page 8.2-14 Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator Previously we calculated the propagation delay time for a nonslewing comparator. If the comparator slews, then the propagation delay time is found from dvi ∆ vi ii = Ci dt = Ci ∆t i i where Ci is the capacitance to ground at the output of the i-th stage The propagation delay time of the i-th stage is, ∆Vi ti = ∆ ti = C i I i The propagation delay time is found by summing the delays of each stage. tp = t1 + t2 + t3 + ··· Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-15 Example 8.2-5 - Calculation of the Propagation Time Delay of a Two-Stage, Open-Loop Comparator For the two-stage comparator shown VDD = 2.5V assume that CI = 0.2pF and CII = 5pF. Also, M6 M3 M4 4.5µm 4.5µm assume that vG1 = 0V and that vG2 has the 38µm 1µm 1µm 1µm waveform shown. If the input voltage is large vo1 vout enough to cause slew to dominate, find the propagation time delay of the rising and falling CI = M2 vG1 M1 3µm 3µm output of the comparator and give the propagation 30µA CII = 0.2pF 1µm 1µm time delay of the comparator. 5pF vG2 vG2 2.5V 0V 0 0.2 0.4 t(µs) 0.6 -2.5V 4.5µm 1µm 234µA 30µA M8 Fig. 8.2-5 4.5µm M5 1µm VSS = -2.5V 35µm 1µm M7 Fig. 8.2-5A Solution The total delay will be given as the sum of the first and second stage delays, t1 and t2, respectively. First, consider the change of vG2 from -2.5V to 2.5V at 0.2µs. From Table 8.2-1, the last row, the initial states of vo1 and vout are +2.5V and -2.5V, respectively. To find the falling delay of the first stage, tf1, requires CI, ∆Vo1, and I5. CI = 0.2pF, I5 = 30µA and ∆V1 can be calculated by finding the trip point of the output stage by setting the current of M6 when saturated equal to 234µA. β6 234·2 2 110·38 = 1.035V 2 (VSG6-|VTP|) = 234µA → VSG6 = 0.7 + Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.035 = 1.465V Chapter 8 - CMOS Comparators (5/1/01) CMOS Analog Circuit Design © P.E. Allen, 2001 Page 8.2-16 Example 8.2-5 - Continued Therefore, ∆V1 = 2.5V - 1.465V = VSG6 = 1.035V. Thus the falling propagation time delay of the first stage is 1.035V tfo1 = 0.2pF 30µA = 6.9ns The rising propagation time delay of the second stage requires the knowledge of CII, ∆Vout, and I6. CII is given as 5pF, ∆ V out = 2.5V (assuming the trip point of the circuit connected to the output of the comparator is 0V), and I6 can be found as follows. When the gate of M6 is at 1.465V, the current is 234µA. However, the output of the first stage will continue to fall so what value should be used for the gate in order to calculate I6? The lowest value of VG6 is given as 2·15 110·3 = -1.00V Let us take the approximate value of VG6 as midway between 1.465V and -1.00V which is 0.232V. Therefore VSG6 = 2.27V and the value of I6 is VG6 = VG1 - VGS1(ISS/2) + VDS2 ≈ -VGS1(ISS/2) = -0.7 - β6 38·50 I6 = 2 (VSG6-|VTP|)2 = 2 (2.27 - 0.7)2 = 2,342µA which is a reminder that the active transistor can generally sink or source more current than the fixed transistor in the class-A inverting stage. The rising propagation time delay for the output can expressed as 2.5V trout = 5pF 2,342µA-234µA = 5.93ns Thus the total propagation time delay of the rising output of the comparator is approximately 12.8ns and most of this delay is attributable to the first stage. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-17 Example 8.2-5 - Continued Next consider the change of vG2 from 2.5V to -2.5V which occurs at 0.4µs. We shall assume that vG2 has been at 2.5V long enough for the conditions of Table 8.2-1 to be valid. Therefore, vo1 ≈ 0V-VGS1(30µA) = -1.13V and vout ≈ VDD. Rather than use Eq. (19) of Sec. 5.1 we have assumed that vout is approximately VDD. The propagation time delays for the first and second stages are calculated as 1.465V-(-1.13V) 2.5V tro1 = 0.2pF tfout = 5pF 234µA = 53.42ns 30µA = 17.3ns The total propagation time delay of the falling output is 70.72ns. Taking the average of the rising and falling propagation time delays gives a propagation time delay for this two-stage, open-loop comparator of about 41.76ns. These values compare favorably with the simulation of the comparator. 3V vout 2V VTRP6 = 1.465V 1V 0V vo1 -1V -2V Rising prop. delay time -3V 200ns 300ns Falling prop. delay time 400ns Time 500ns 600ns Fig. 8.2-6 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-18 Design of a Two-Stage, Open-Loop Comparator Table 8.2-2 Design of the Two-Stage, Open-Loop Comparator of Fig. 8.2-3 for a Linear Response. Specifications: tp, CII ,Vin(min), VOH, VOL, Vicm+, Vicm-, and overdrive Step Design Relationships 1 1 |pI| = |pII| = , tp mk 2 W6 L6 = 3 4 |pII|CII and I7 = I6 = λN+λP W7 2·I7 and L = ˚ 7 KP’(VSD6 KN’(VDS7(sat))2 2CI Guess CI as 0.1pF to 0.5pF ∴ I5 = I7 C II 2·I6 (sat))2 W 3 W4 L3 = L4 = 5 gm1 = 6 I5 KP’(VSG3-|VTP |)2 Av(0)(gds2+gds4)(gds6+gds7) W 1 W 2 gm12 L1 = L2 = K N I5 gm6 Find CI and check assumption CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 7 Constraints: Technology, VDD and VSS W5 2·I5 VDS5(sat) = Vicm--VGS1-VSS L = 2 5 K ’(V N DS5(sat)) Chapter 8 - CMOS Comparators (5/1/01) Comments Choose m = 1 VSD6(sat) = VDD-VOH VDS7(sat) = VOL - VSS A result of choosing m = 1. Will check CI later VSG3 = VDD-Vicm++VTN gm6 = 2KP’W6I6 VOH +VOL Av(0) = V (min) L6 in If CI is greater than the guess in step 3, then increase CI and repeat steps 4 through 6 If VDS5(sat) is less than 100mV, increase W1/L1. © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-19 Example 8.2-6 - Design of the Two-Stage, Open-Loop Comparator of Fig. 8.2-3 for a Linear Response. VDD Assume the specifications of the comparator shown are given below. i4 i3 VOH = 2V VOL = -2V tp = 50ns M3 M4 vo1 M6 VSS = -2.5V CII = 5pF VDD = 2.5V CI i i 1 Vin(min) = 1mV Vicm+ = 2V Vicm- = -1.25V vG1 M1 Also assume that the overdrive will be a factor of 10. Use this architecture to achieve the above specifications and + assume that all channel lengths are to be 1µm. VBias Solution Following the procedure outlined in Table 8.2-2, we choose m = 1 to get 109 = 6.32x106 rads/sec |p I| = |p II| = 50 10 This gives 6.32x106·5x10-12 = 351µA → I6 = I7 = 400µA I6 = I7 = 0.04+0.05 Therefore, W7 W6 2·400 2·400 = = 64 and 2 L 6 (0.5) ·50 L 7 = (0.5)2·110 = 29 Chapter 8 - CMOS Comparators (5/1/01) 2 vout vG2 M2 CII ISS M7 M5 VSS Fig. 8.2-3 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-20 Example 8.2-6 - Continued Next, we guess CI = 0.2pF. This gives I 5 = 32µA and we will increase it to 40µA for a margin of safety. Step 4 gives VSG3 as 1.2V which results in W3 W4 W3 W4 40 → L 3 = L 4 = 50(1.2-0.7)2 = 3.2 L3 = L4 = 4 The desired gain is found to be 4000 which gives an input transconductance of 4000·0.09·20 = 162µS 44.44 This gives the W/L ratios of M1 and M2 as W 1 W 2 (162)2 L 1 = L 2 = 110·40 = 5.96 → gm1 = W1 W2 L1 = L2 = 6 To check the guess for CI we need to calculate it which is done as CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 = 0.9fF+1.3fF+119.5fF+20.4fF+36.8fF = 178.9fF which is less than what was guessed so we will make no changes. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-21 Example 8.2-6 - Continued Finally, the W/L value of M5 is found by finding V GS1 as 0.946V which gives VDS5(sat) = 0.304V. This gives W5 2·40 L 5 = (0.304)2·110 = 7.87 ≈ 8 Obviously, M5 and M7 cannot be connected gate-gate and source-source. The value of I 5 and I 7 must be derived separately as illustrated below. The W values are summarized below assuming that all channel lengths are 1µm. W 3 =W 4 = 4µm W5 = 8µm W 1 = W 2 = 6µm W6 = 64µm W7 = 29µm VDD 8/1 10µA 2/1 M10 M11 10µA M5 M9 2/1 M8 2/1 40µA 40µA 8/1 M12 3/1 M7 400µA 29/1 VSS Fig. 8.2-7 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-22 Design of a Two-Stage Comparator for a Slewing Response Table 8.2-3 Design of the Two-Stage, Open-Loop Comparator of Fig. 8.2-3 for a Slewing Response. Specifications: tp, CII ,Vin(min), VOH, VOL, Vicm+, VicmStep Constraints: Technology, VDD and VSS Design Relationships Comments 1 dvout CII(VOH-VOL) I7 = I6 = C II· dt = tp Assume the trip point of the output is (VOHVOL)/2. 2 2·I6 W7 2·I7 W6 and L = L6 = K ’(V 2 2 ˚ 7 K ’(V P SD6(sat)) N DS7(sat)) VSD6(sat) = VDD-VOH 3 Guess CI as 0.1pF to 0.5pF 2CI ∴ I 5 = I7 C VDS7(sat) = VOL - VSS Typically 0.1pf<CI<0.5pF II 4 dvo1 CI(VOH-VOL) I5 = CI· dt ≈ tp Assume that vo1 swings between VOH and VOL. 5 W 3 W4 I5 L3 = L4 = KP’(VSG3-|VTP|)2 VSG3 = VDD-Vicm++VTN 6 gm1 = 7 Av(0)(gds2+gds4)(gds6+gds7) gm6 W 1 W 2 gm12 L1 = L2 = K N I5 Find CI and check assumption CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 8 W5 2·I5 VDS5(sat) = Vicm--VGS1-VSS L = 5 KN’(VDS5(sat))2 Chapter 8 - CMOS Comparators (5/1/01) VOH+VOL Av(0) = V (min) in If CI is greater than the guess in step 3, increase the value of CI and repeat steps 4 through 6 gm6 = 2KP’W 6I6 L6 If VDS5(sat) is less than 100mV, increase W1/L1. © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-23 Example 8.2-7 - Design of the Two-Stage, Open-Loop Comparator for a Slewing Response Assume the specifications of Fig. 8.2-3 are given below. tp = 50ns VOH = 2VVOL = -2V VDD = 2.5V VSS = -2.5VCII = 5pF Vin(min) = 1mV Vicm+ = 2VVicm- = -1.25V Design a two-stage, open-loop comparator using the circuit of Fig. 8.2-3 to the above specifications and assume all channel lengths are to be 1µm. Solution Following the procedure outlined in Table 8.2-3, we calculate I6 and I7 as 5x10-12·4 = 400µA I6 = I7 = 50x10-9 Therefore, W7 W6 2·400 2·400 L 6 = (0.5)2·50 = 64 and L 7 = (0.5)2·110 = 29 Next, we guess CI = 0.2pF. This gives 0.2pF(4V) I5 = 50ns = 16µA → Step 5 gives VSG3 as 1.2V which results in W3 W4 20 L 3 = L 4 = 50(1.2-0.7)2 = 1.6 I5 = 20µA W 3 W4 L3 = L4 = 2 → Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.2-24 Example 8.2-7 - Continued The desired gain is found to be 4000 which gives an input transconductance of 4000·0.09·10 = 81µS gm1 = 44.44 This gives the W/L ratios of M1 and M2 as W3 W4 W1 W2 (81)2 L = L = 110·40 = 1.49 → L = L =2 3 4 1 2 To check the guess for CI we need to calculate it which done as CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 = 0.9fF+0.4fF+119.5fF+20.4fF+15.3fF = 156.5fF which is less than what was guessed. Finally, the W/L value of M5 is found by finding V GS1 as 1.00V which gives VDS5(sat) = 0.25V. This gives W5 2·20 L 5 = (0.25)2·110 = 5.8 ≈ 6 As in the previous example, M5 and M7 cannot be connected gate-gate and source-source and a scheme like that of Example 8.2-6 must be used. The W values are summarized below assuming that all channel lengths are 1µm. W3 =W4 = 4µm W 5 = 6µm W 6 = 64µm W 7 = 29µm W1 = W2 = 2µm Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.3-1 SECTION 8.3 - OTHER OPEN-LOOP COMPARATORS Push-Pull Comparators Clamped: VDD M6 M4 M8 M3 vin + M1 vout M2 CL M5 M9 + VBias - M7 VSS Fig. 8.3-1 Comments: • Gain reduced → Larger input resolution • Push-pull output → Higher slew rates Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.3-2 Push-Pull Comparators - Improved Cascode output stage: VDD M6 M4 M15 M8 M3 vin + M1 M2 M14 R1 M9 M7 R2 vout M12 M10 M5 + VBias - CII M11 M13 VSS Fig. 8.3-2 Comments: • Can also use the folded cascode architecture • Cascode output stage result in a slow linear response (dominant pole is small) • Poorer noise performance Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.3-3 Comparators that Can Drive Large Capacitive Loads VDD M8 M3 M10 M4 M6 vin + M1 vout M2 CII + VBias - M7 M5 M9 M11 VSS Fig. 8.3-3 Comments: • Slew rate = 3V/µs into 50pF • Linear rise/fall time = 100ns into 50pF • Propagation delay time ≈ 1µs • Loop gain ≈ 32,000 V/V Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.3-4 Self-Biased Differential Amplifier† VDD VBias VDD M6 M6 M4 M3 M4 M3 vin+ vin- vout vin+ M1 M1 Extremely large sourcing current vinM2 M2 M5 VBias M5 VSS VSS Fig. 8.3-4 Advantage: Large sink or source current with out a large quiescent current. Disadvantage: Poor common mode range (vin+ slower than vin-) † M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb. 1991, pp. 165-168. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-1 SECTION 8.4 IMPROVING THE PERFORMANCE OF THE OPEN-LOOP COMPARATORS Autozeroing Techniques Use the comparator as an op amp to sample the dc input offset voltage and cancel the offset during operation. Ideal Comparator Ideal Comparator - Ideal Comparator vIN - + + VOS VOS - vOUT + - + VOS VOS VOS + -C CAZ AZ Model of Comparator. Autozero Cycle Comparison Cycle Fig. 8.4-1 Comments: • The comparator must be stable in the unity-gain mode (self-compensating comparators are good, the twostage op comparator would require compensation to be switched in during the autozero cycle.) • Complete offset cancellation is limited by charge injection Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-2 Differential Implementation of Autozeroed Comparators vIN- φ 1Ideal Comparator φ2 - φ1 vIN+ φ2 vOUT + VOS CAZ φ1 Differential Autozeroed Comparator Chapter 8 - CMOS Comparators (5/1/01) + VOS - + vOUT = VOS VOS Comparator during φ1 phase vINvOUT + + vIN + VOS VOS Comparator during φ2 phase Fig. 8.4-2 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-3 Single-Ended Autozeroed Comparators Noninverting: φ2 vIN φ1 CAZ φ2 - φ1 + vOUT φ1 Fig. 8.4-3 Inverting: vIN CAZ φ2 - φ1 φ1 vOUT + Fig. 8.4-4 Comment on autozeroing: Need to be careful about noise that gets sampled onto the autozeroing capacitor and is present on the comparison phase of the process. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-4 Influence of Input Noise on the Comparator Comparator without hysteresis: Comparator threshold vin t VOH vout t VOL Fig. 8.4-6A Comparator with hysteresis: vin VTRP+ t VTRPVOH vout t VOL Chapter 8 - CMOS Comparators (5/1/01) Fig. 8.4-6B © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-5 Use of Hysteresis for Comparators in a Noisy Environment Transfer curve of a comparator with hysteresis: vOUT vOUT VOH VTRP+ vIN VTRP- VOH R1 (V -V ) R2 OH OL 0 0 VTRP+ vIN VTRP- VOL VOL Counterclockwise Bistable Clockwise Bistable Fig. 8.4-5 Hysteresis is achieved by the use of positive feedback • Externally • Internally Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-6 Noninverting Comparator using External Positive Feedback Circuit: vOUT R2 vIN R1 + vOUT - R1VOL R2 VOH R1 (V -V ) R2 OH OL 0 0 Fig. 8.4-7 R1VOH R2 vIN VOL Upper Trip Point: Assume that vOUT = VOL, the upper trip point occurs when, R1 R2 → 0 = R +R V OL + R +R VTRP+ R1 VTRP+ = - R V OL Lower Trip Point: Assume that vOUT = VOH, the lower trip point occurs when, R1 R2 → 0 = R +R VOH + R +R VTRP 1 2 1 2 R1 VTRP- = - R VOH 1 2 1 2 2 2 Width of the bistable characteristic: R 1 ∆Vin = VTRP+-VTRP- = R ( VOH -VOL) 2 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-7 Inverting Comparator using External Positive Feedback Circuit: vOUT vIN - vOUT + R1 R2 VOH R1 (V -V ) R1+R2 OH OL 0 0 R1VOL R1+R2 VOL vIN R1VOH R1+R2 Fig. 8.4-8 Upper Trip Point: R1 vIN = VTRP+ = R +R VOH 1 2 Lower Trip Point: R1 vIN = VTRP- = R +R VOL 1 2 Width of the bistable characteristic: R1 ∆Vin = VTRP+-VTRP- = R +R ( VOH -VOL) 1 2 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-8 Horizontal Shifting of the CCW Bistable Characteristic Circuit: vOUT VOH R2 vIN R1 + vOUT R1+R2 R1 VREF 0 0 - VREF Fig. 8.4-9 R1 (V -V ) R2 OH OL R1|VOL| R2 VOL vIN R1VOH R2 Upper Trip Point: R1 R2 VREF = R +R V OL + R +R VTRP+ 1 2 1 2 Lower Trip Point: R1 R2 VREF = R +R VOH + R +R VTRP 1 2 1 2 → R1 R1+R2 VTRP+ = R VREF - R V OL 1 2 → R1 R1+R2 VTRP- = R VREF - R VOH 1 2 Shifting Factor: R1+R2 R V 1 REF Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-9 Horizontal Shifting of the CW Bistable Characteristic Circuit: vIN vOUT - vOUT + R1 VOH R2 R1 (V -V ) R1+R2 OH OL R1 R1+R2VREF 0 0 VREF VOL R1|VOL| R1+R2 vIN R1VOH R1+R2 Fig. 8.4-10 Upper Trip Point: R1 R1 vIN = VTRP+ = R +R VOH + R +R VREF 1 2 1 2 Lower Trip Point: R1 R1 vIN = VTRP- = R +R V OL + R +R VREF 1 2 1 2 Shifting Factor: R1 R +R VREF 1 2 Chapter 8 - CMOS Comparators (5/1/01) CMOS Analog Circuit Design © P.E. Allen, 2001 Page 8.4-10 Example 8.4-1 Design of an Inverting Comparator with Hysteresis Use the inverting bistable to design a high-gain, open-loop comparator having an upper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V. Solution Putting the values of this example into the above relationships gives R1 R1 1 = R +R 2 + R +R V REF 1 2 1 2 and R1 R1 0 = R +R (-2) + R +R V REF 1 2 1 2 Solving these two equations gives 3R1 = R2 and VREF = 2V. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-11 Hysteresis using Internal Positive Feedback Simple comparator with internal positive feedback: VDD M3 IBias M6 M4 M7 vo1 vi1 vo2 M2 M1 M8 vi2 M5 Fig. 8.4-11 VSS Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-12 Internal Positive Feedback - Upper Trip Point Assume that the gate of M1 is on ground and the input to M2 is much smaller than zero. The resulting circuit is: M1 on, M2 off → M3 and M6 on and M4 and M7 off. ∴ vo2 is high. VDD vo1 W6/L6 M6 would like to source the current i6 = W L i1 3 3 As vin begins to increase towards the trip point, the current flow through M2 increases. When i2 = i6, the upper trip point will occur. ∴ W6/L6 W6/L6 i5 = i1+i2 = i3+i6 = i3 + W /L i3 = i3 1 + W /L 3 3 3 3 M3 M6 M7 M4 M1 M2 i2 = i6 i1 = i3 vo2 vin M5 I5 VSS Fig. 8.4-12A which gives i5 i1 = i3 = 1 + [(W /L )/(W /L )] 6 6 3 3 Also, i2 = i5 - i1 = i5 - i3 Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives VTRP+ = vGS2 - vGS1 = 2i2 β2 + VT2 - Chapter 8 - CMOS Comparators (5/1/01) 2i1 β1 - VT1 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-13 VDD Internal Positive Feedback - Lower Trip Point Assume that the gate of M1 is on ground and the input to M2 is much greater than zero. The resulting circuit is: M2 on, M1 off → M4 and M7 on and M3 and M6 off. ∴ vo1 is high. vo1 vi1 W7/L7 M7 would like to source the current i7 = W /L i2 M3 M6 M1 M7 M4 M2 vo2 vi1 i2 = i4 i1 = i7 vin 4 4 I5 As vin begins to decrease towards the trip point, the current flow through M1 increases. When i1 = i7, the lower trip point will occur. ∴ M5 VSS W7/L7 W7/L7 i5 = i1+i2 = i7+i4 = W /L i4 + i4 = i4 1 + W /L 4 4 Fig. 8.4-12B which gives 4 4 i5 i2 = i4 = 1 + [(W /L )/(W /L )] 7 7 4 4 Also, i1 = i5 - i2 = i5 - i4 Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives VTRP- = vGS2 - vGS1 = 2i2 β2 + VT2 - 2i1 β1 - VT1 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-14 Example 8.4-2 - Calculation of Trip Voltages for a Comparator with Hysteresis Consider the circuit shown. Using the transistor VDD device parameters given in Table 3.1-2 calculate the positive and negative threshold points if the device lengths M3 M6 M7 are all 1 µm and the widths are given as: W 1 = W 2 = W 6 IBias = W 7 = 10 µm and W 3 = W 4 = 2 µm. The gate of M1 is vo1 tied to ground and the input is the gate of M2. The current, i5 = 20 µA. Simulate the results using PSPICE. Solution To calculate the positive trip point, assume that the input has been negative and is heading positive. (W/L)6 i6 = (W/L) i3 = (5/1)(i3) 3 vi1 M8 M4 vo2 M2 M1 M5 VSS Fig. 8.4-11 i5 20 µA i3 = 1 + [(W/L) /(W/L) ] = i1 = 1 + 5 = 3.33 µA 6 3 i2 = i5 − i1 = 20 − 3.33 = 16.67 µA 1/2 2i1 1/2 2·3.33 vGS1 = β + V T1 = (5)110 + 0.7 = 0.81V 1 2·16.67 1/2 2i2 1/2 vGS2 = β + V T2 = (5)110 + 0.7 = 0.946V 2 VTRP+ ≅ vGS2 − vGS1 = 0.946 − 0.810 = 0.136V Chapter 8 - CMOS Comparators (5/1/01) vi2 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-15 Example 8.4-2 - Continued Determining the negative trip point, similar analysis yields i4 = 3.33 µA i1 = 16.67 µA vGS2 = 0.81V vGS1 = 0.946V VTRP- ≅ vGS2 − vGS1 = 0.81 − 0.946 = −0.136V PSPICE simulation results of this circuit are shown below. 2.6 2.4 2.2 2 vo2 1.8 (volts) 1.6 1.4 1.2 1 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 vin (volts) 0.3 0.4 0.5 Fig. 8.4-13 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-16 Complete Comparator with Internal Hysteresis VDD M3 IBias M6 M4 M7 M9 M8 vi1 M2 M1 M10 M8 vout M11 M5 VSS Chapter 8 - CMOS Comparators (5/1/01) vi2 Fig. 8.4-14 © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-17 Schmitt Trigger The Schmitt trigger is a circuit that has better defined switching points. Consider the following circuit: How does this circuit work? VDD Assume the input voltage, vin, is low and the output voltage, vout , is high. M5 M4 vin M3 M2 vout M6 ∴ M3, M4 and M5 are on and M1, M2 and M6 are off. When vin is increased from zero, M2 starts to turn on causing M3 to start turning off. Positive feedback causes M2 to turn on further and eventually both M1 and M2 are on and the output is at zero. The upper switching point, VTRP+ is found as follows: When vin is low, the voltage at the source of M2 (M3) is vS2 = VDD-VTN3 M1 VTRP+ is defined as the point when M2 turns on given as VTRP+ = VTN2 + vS2 Fig. 8.4-15 VTRP+ occurs at the point where the input voltage causes the current in M3 to equal the current in M1. Thus, iD1 = β1( VTRP+ - VTN1)2 = β3( VDD - vS2- VTN3)2 = iD3 which can be written as, assuming that VTN2 = VTN3, β1( VTRP+ - VTN1)2 = β3( VDD – VTRP+)2 VTN1 + ⇒ VTRP+ = 1+ β3 β1 VDD β3 β1 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.4-18 Schmitt Trigger – Continued The switching point, VTRP- is found in a similar manner and is: β5( VDD - VTRP- - VTP5)2 = β6( VTRP-)2 ⇒ VTRP- = β5 β6 (VDD - VTP5) 1+ β5 β6 The bistable characteristic is, vout VDD 0 0 VTRP- VTRP+ VDD vin Fig. 8.4-16 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-1 SECTION 8.5 - DISCRETE-TIME COMPARATORS Switched Capacitor Comparator V1 φ1 V2 φ2 φ1 VC - + C Cp + VOS + V1 - VOS + - Vout - A V2 - + C - + VOS - - Cp + VOS - + Vout A Equivalent circuit when the φ2 switches are closed A switched capacitor comparator Fig. 8.5-1 φ1 Phase: The V1 input is sampled and the dc input offset voltage is autozeroed. VC(φ1) = V1 - VOS and VCp(φ1) = VOS φ2 Phase: V2C (V1-VOS)C VOSCp + C+C + AVOS Vout(φ2) =-A C+C - C+C p p p Cp C C C = -A (V2-V1) C+C + VOSC+C + C+C + AVOS = -A(V2-V1) C+C ≈ A(V1-V2) p p p p if Cp is smaller than C. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-2 Differential-In, Differential-Out Switched Capacitor Comparator + φ1 φ2 C +- vin - φ1 - + φ1 φ2 C φ1 + vout - Fig. 8.5-2 Comments: • Reduces the influence of charge injection • Eliminates even harmonics Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-3 Regenerative Comparators Regenerative comparators use positive feedback to accomplish the comparison of two signals. Latches have a faster switching speed that the previous bistable comparators. NMOS and PMOS latch: VDD I1 VDD I2 M2 M1 vo1 vo1 vo2 I1 M2 M1 vo2 I2 NMOS latch PMOS latch Fig. 8.5-3 How is the input applied to a latch? The inputs are initially applied to the outputs of the latch. Vo1’ = initial input applied to vo1 Vo2’ = initial input applied to vo2 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-4 Step Response of a Latch VDD I1 VDD I2 + vo2 vo1 M1 Vo2 V ' gm1Vo2 R1 so1 - M2 + C1 Vo1 gm2Vo1 R2 - C2 Vo2' s + Vo2 Fig. 8.5-4 where Ri and Ci are the resistance and capacitance seen to ground from the i-th transistor. Nodal equations: Vo1’ gm1Vo2+G1Vo1+sC1Vo1- s = gm1Vo2+G1Vo1+sC1V o1-C1Vo1’ = 0 Vo2’ gm2Vo1+G2Vo2+sC2Vo2- s = gm2Vo1+G2Vo2+sC2V o2-C2Vo2’ = 0 Solving for Vo1 and Vo2 gives, R1C1 gm1R1 gm1R1 τ1 Vo1 = sR C +1 Vo1’ - sR C +1 V o2 = sτ +1 Vo1’ - sτ +1 V o2 1 1 1 1 1 1 R2C2 gm2R2 gm2R2 τ2 Vo2 = sR C +1 Vo2’ - sR C +1 V o1 = sτ +1 Vo2’ - sτ +1 V o1 2 2 2 2 2 2 Defining the output, ∆Vo, and input, ∆Vi, as ∆Vo = Vo2-Vo1 and Chapter 8 - CMOS Comparators (5/1/01) ∆Vi = Vo2’-Vo1’ © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-5 Step Response of the Latch - Continued Solving for ∆Vo gives, gmR τ ∆Vo = Vo2-Vo1 = sτ+1 ∆ V i + sτ+1 ∆ V o or where τ ∆Vi τ ∆Vi 1-gmR τ’ ∆Vi ∆ V o = sτ+(1-g R) = sτ = sτ’+1 m 1-gmR + 1 τ τ’ = 1-g R m Taking the inverse Laplace transform gives ∆vo(t) = ∆Vi’ e-t/τ = ∆Vi e-t(1-gmR) /τ ≈ egmRt/τ∆Vi, Define the latch time constant as 0.67WLCox C τ τL ≈ g R = g = = 0.67Cox m m 2K’(W/L)I if C ≈ Cgs. ∆Vout(t) = et/τL ∆Vi ∴ if gmR >>1. WL3 2K’I Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-6 Step Response of a Latch - Continued Normalize the output voltage by (VOH-VOL) to get ∆Vout(t) ∆Vi t/τ VOH-VOL = e L VOH-VOL which is plotted as, 1 0.5 0.4 0.3 0.8 ∆Vout VOH-VOL 0.2 0.1 0.05 0.6 ∆Vi VOH-VOL 0.03 0.01 0.4 0.005 0.2 0 0 1 2 t τL 3 4 5 Fig. 8.5-5 VOH- VOL The propagation delay time is tp = τL ln 2∆V i Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-7 Example 8.5-1 - Time domain characteristics of a latch. Find the time it takes from the time the latch is enabled until the output voltage, ∆Vout, equals VOH-VOL if the W/L of the latch NMOS transistors is 10µm/1µm and the latch dc current is 10µA when ∆ V i = 0.1(VOH-VOL) and ∆ V i = 0.01(VOH-VOL). Find the propagation time delay for the latch for each of these conditions. Solution The transconductance of the latch transistors is g m = 2·110·10·10 = 148µS The output conductance is 0.4µS which gives gmR of 59.2V/V. Since g m R is greater than 1, we can use the above results. Therefore the latch time constant is found as (10·1)x10-18 = 108ns 2·110x10-6·10x10-6 If we assume that the propagation time delay is the time when the output is 0.5(VOH-VOL), then using the above results or Fig. 8.5-5 we find for ∆Vi = 0.01(VOH-VOL) that tp = 3.91τL = 422ns and for ∆ V i = 0.1(VOHVOL) that tp = 2.3τL = 174ns. τL = 0.67Cox WL3 -4 2K’I = 0.67(24x10 ) If we assume that the propagation time delay is the time for the output to reach (VOH-VOL), then for ∆Vi = 0.01(VOH-VOL) that tp = 4.602τL = 497ns and for ∆Vi = 0.1(VOH-VOL) that tp = 2.306τL = 249ns. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-8 Comparator using a Latch with a Built-In Threshold† How does it operate? 1.) Devices in shaded region operate in the triode φ1 M7 region. Latch M9 /Reset 2.) When the latch/reset goes high, the upper crossφ1 M5 coupled inverter-latch regenerates. The drain currents of M5 and M6 are steered to obtain a final state M3 determined by the mismatch between the R1 and R2 VDD φ1 M10 Latch /Reset φ1 M6 M8 resistances. W2 W1 1 + R1 = K N L (vin - VT) + L (VREF - VT) M1 M4 vout+ vout- R1 M2 M2 vin+ and W2 W1 1 + R2 = K N L (vin - VT) + L (VREF - VT) R2 M1 vin- VREF- VREF+ Fig. 8.5-6 3.) The input voltage which causes R1 and R2 to be equal is given by vin(threshold) = (W2/W1)VREF W2/W1 = 1/4 generates a threshold of ±0.25VREF. Performance → 20Ms/s & 200µW † T.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March 1995. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-9 Simple, Low Power Latched Comparator† VDD φ1 M10 φ1 M5 φ1 M6 vout+ voutM4 M3 vin+ φ1 M8 M7 M9 M1 vin- M2 Fig. 8.5-7 Dissipated 50µW when clocked at 2MHz. † A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.5-10 Dynamic Latch Circuit: VDD φLatch M6 M8 VREF M4 + vout M3 vin vout- M7 M1 φLatch M2 M5 ; ;; ; ; ;; ; ; ;; ;;; ;;; Fig. 8.5-8 Number of Samples Input offset voltage distribution: 20 σ = 5.65 10 0 -15 L = 1.2µm (0.6µm Process) -10 -5 0 5 10 Input offset voltage (mV) 15 Fig. 8.5-9 Power dissipation/sampling rate = 4.3µW/Ms/s Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-1 SECTION 8.6 - HIGH-SPEED COMPARATORS Conceptual Illustration of a Cascaded Comparator How does a cascaded, high-speed comparator work? A0 sT+1 A0 sT+1 A0 sT+1 A0 sT+1 A0 sT+1 A0 sT+1 Linear small signal Linear small signal Linear & large signal Large signal small C Large signal bigger C Large signal big C Fig. 8.6-1 Assuming a small overdrive, 1.) The initial stage build the driving capability. 2.) The latter stages swing rail-to-rail and build the ability to quickly charge and discharge capacitance. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-2 Minimizing the Propagation Delay Time in Comparators Fact: • The input signal is equal to Vin(min) for worst case • Amplifiers have a step response with a negative argument in the exponential • Latches have a step response with a positive argument in the exponential Result: Use a cascade of linear amplifier to quickly build up the signal level and apply this amplified signal level to a latch for quick transition to the full binary output swing. Illustration of a preamplifier and latch cascade: vout VOH Latch Preamplifier VX VOL t1 t2 t Fig. 8.6-2 Minimization of tp: Q. If the preamplifer consists of n stages of gain A having a single-pole response, what is the value of n and A that gives minimum propagation delay time? A. n = 6 and A = 2.62 but this is a very broad minimum and n is usually 3 and A ≈ 6-7 to save area. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-3 Fully Differential, Three-Stage Amplifier and Latch Comparator Circuit: FB Reset Cv1 Reset C1 Cv3 + -+ Cv2 C2 FB FB Cv5 + - + -+ -+ Reset Reset Cv4 FB + Latch vout - Reset Cv6 FB FB + vin - Clock Fig. 8.6-3 Comments: • Autozero and reset phase followed by comparison phase • More switches are needed to accomplish the reset and autozero of all preamplifiers simultaneously • Can run as high as 100Msps Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-4 Preamplifier and Latch Circuits VDD Gain: gm1 gm2 Av = - g = - g = m3 m4 M3 KN’(W1/L1) Kp’(W3/L3) Dominant Pole: gm3 gm4 |pdominant| = C = C where C is the capacitance seen from the output nodes to ground. If (W1/L1)/(W3/L3) = 100 and the bias current is 100µA, then A = -3.85 and the bandwidth is 15.9MHz if C = 0.5pF. FB M4 Q Reset Q FB M1 M5 M6 M2 Latch Enable Latch Preamplifier VBias Fig. 8.6-4 Comments: • If a buffer is used to reduce the output capacitance, one must take into account the loss of the buffer. • The use of a preamplifier before the latch reduces the latch offset by the gain of the preamplifier so that the offset is due to the preamplifier only. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-5 An Improved Preamplifier Circuit: VDD VBiasP vout- M3 VBiasP M4 M6 M5 vout+ Reset M12 M10 FB M11 FB M8 M7 VBias vin+ vin- M2 M1 VBiasN M9 Fig. 8.6-5 Gain: gm1 KN’(W1/L1)I1 KN’(W1/L1) =Av = - g = K K ’(W /L )I m3 P 3 3 3 P’(W3/L3) If I5 = 24I3, the gain is increased by a factor of 5 I5 1+I 3 Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-6 Charge Transfer Preamplifier The preamplifier can be replaced by the charge transfer circuit shown. VPR vin=VREF vin=VREF VPR VREF-VT+∆V S2 vin-VT S1 CT CO + vout - Charge transfer amplifier. CT vin = VREF+∆V CO + vout =VPR - Precharge phase. CT CO + vout =VPR -CT ∆V CO Amplification phase. Fig. 8.6-6 Comments: • Only positive values of voltage will be amplified. • Large offset voltages result as a function of the subthreshold current. Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-7 A CMOS Charge Transfer Preamplifier Circuit: VDD VDD CT VPR S1 M2 S3 S2 vin CT S3 S1 M1 vout CO Fig. 8.6-7 Comments: • NMOS and PMOS allow both polarities of input • CMOS switches along with dummy switches reduce the charge injection • Switch S3 prevents the subthreshold current influence • Used as a preamplifier in a comparator with 8-bit resolution at 20Msps and a power dissipation of less than 5µW Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-8 A High-Speed Comparator Circuit: VDD Self-biased diff amp Output Driver Preamp vout vin+ vin- IBias Latch Fig. 8.6-8 Comments: • Designed to have a tp = 10ns with a 5pF load and a 10mV overdrive • Not synchronous • Comparator gain is greater than 2000V/V and the quiescent current was 100µA Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001 CMOS Analog Circuit Design Page 8.6-1 SECTION 8.7 - SUMMARY Types of Comparators Presented • High-gain, open-loop • Improved high-gain, open-loop, comparators Hysteresis Autozeroing • Regenerative comparators • Discrete-time comparators Performance Characterization • Propagation delay time • Binary output swing • Input resolution and/or gain • Input offset voltage • Power dissipation Important Principles • The speed of the comparator depends on the linear and slewing responses • The dc input offset voltage depends on the matching and can be reduced by autozeroing. Charge injection is the limit of autozeroing • The gain of the comparator should be large enough for a binary output when vin = Vin(min) • In cascaded comparators, the early stages should have wide bandwidth and the latter stages high slew rate Chapter 8 - CMOS Comparators (5/1/01) © P.E. Allen, 2001